The present invention relates to a system for observing signal waveforms, and relates to such a system which is called a logic scope or a logic analyzer.
That kind of signal observation system has a memory for storing a signal to be observed, and displays a plurality of waveforms simultaneously on a CRT screen, therefore, that system is useful for the development of an electronic apparatus, and/or the maintenance or repair of such an apparatus.
The prior waveform observation system, or a logic analyzer has been shown in the Japanese patent publication No. 34903/80. FIG. 1 is the block diagram of that prior logic analyzer.
In FIG. 1, the reference numeral 1 is an input terminal for accepting signals or waveforms to be analyzed. The input terminal 1 has a plurality of terminals (for instance 8 terminals) in order to analyze simultaneously a plurality of waveforms. The reference numeral 2 is a comparator which compares the level of a signal of the input terminal 1 with the threshold level which is supplied by the reference voltage source 3, and said comparator 2 provides a digital output signal according to the result of the comparison. That comparator 2 is installed for each channel of the input waveforms. The reference numeral 4 is a memory for storing a digital output signal of said comparator 2, and said memory 4 is also provided for each channel. The memory 4 writes the signal with the writing clock signal generated by the clock signal generator 6, and reads the content repetitively with the reading clock signal. The reference numeral 5 is a control counter which provides the address information of the memory 4 according to the writing clock signal generated by the clock signal generator 6. That control counter 5 also provides a write-read switching signal after the predetermined delay time determined by the trigger delay circuit 8 when the trigger circuit 7 provides a trigger signal to said control counter 5. Said write-read switching signal is applied to the clock signal generator 6, and then, the writing clock phase is switched to the reading clock phase. The switch SW is provided in order to trigger the control counter 5 by an external trigger signal.
The reference numerals 10 and 11 are a condition set switch and a gate circuit (condition detection circuit), respectively, and are shown in FIG. 2 in detail. That condition set switch and gate circuit are provided for each channel. Each condition set switch (10-1, 10-2, . . . , 10-n) has a switch with three contacts, which correspond to (1) the logic value "1", (2) DONT CARE "X" which does not care whether the input digital value is "1" or "0", and (3) the digital value "1". The first and the third contacts "0" and "1" provide the digital value "0" when closed, and provide the digital value "1" when opened. The gate circuits (11-1, 11-2, 11-3, . . . , 11-n) which relate to the corresponding switches (10-1, 10-2, . . . , 10-n) function (1) to invert the output polarity of the memory 4, (2) to pass the output of the memory 4 without inverting the same, or (3) to stop the output of the memory 4 and prevent the same, according to the status of the switches 10. The AND circuit 12 functions to detect the data which satisfies the conditions defined by the switches 10.
The numeral 14 is a channel selector, which receives the outputs of the memory 4, and the output of the AND circuit 12 through the switch 13. The numeral 15 is a channel counter, which provides the channel selection signal to have the channel selector 14 select the designated channel and output the content of the memory 4, every time the control counter 5 designates the final address for each memory 4. The Y-axis signal generator 16 provides the Y-axis signal to the CRT 19 (cathode ray tube) according to the outputs of the channel selector 14 and the channel counter 15. The X-axis signal and the Z-axis signal are provided by the X-axis signal generator 17 and the Z-axis signal generator 18, respectively, according to the count content of the control counter 5.
It is supposed in FIG. 1 that the number of channels is 8. Each of the input signals at the input terminal 1 is compared with the threshold level in the comparators 2, and is converted to the digital value which takes 1 or 0. The converted value is sampled by each write clock signal, and the sampled values of 8 channels are stored in the memory 4 simultaneously. Upon the completion of the write operation to the memory 4, the trigger circuit 7 generates a trigger signal, which changes the operation mode from the write mode to the read mode, in which the content of the memory 4 is read out. When the switch 13 contacts the contact (a) in the read mode, the 8 channels of the data in the memory 4 are indicated on the screen of the CRT as shown in FIG. 3A.
Next, it is assumed that the switch 13 contacts the contact (b) in the indication status of FIG. 3A, and the switches (10-1, 10-2, . . . , 10-n) set the logic conditions of each channel. For instance, if the channels 1 and 3 are set to "1" by the switches 10, and other channels are set to "x" (don't care), then, the indication of the 8'th channel is replaced by the time sequence of FIG. 3B, which satisfies the logic conditions set by the switches 10.
Accordingly, said prior art of Japanese patent publication No. 34903/80 is useful to analyze the logic signals, and to find out the particular combination of the logic conditions.
However, said prior art has the disadvantages that the logic statuses to be analyzed are restricted only to "1", "0", and "x" (don't care), and the transition of the logic status (from "0" to "1", and from "1" to "0") is not detected. Thus, due to the lack of the detection of the logic changes, said prior apparatus is useless for some purposes.